Intel today revealed Crescent Island’s official product name at the OCP Global Summit. Intel GPU D-series is built on the Xe3P architecture, supporting up to 480GB LPDDR5X memory, 1.5TB/s memory bandwidth and 1.3 petaflops of FP8 compute, packaged as a 350W air-cooled PCIe add-in card. The 480GB memory capacity applies to partner-manufactured boards; Intel’s own branded variant features 160GB. Intel notes customer sampling is underway with server OEMs, ODMs, neocloud providers and independent software vendors. The accompanying render released alongside the announcement bears the label GPU D270, the first part number tied to this product family.

Xe3P Architecture Targets Memory-Bound Inference

Intel first introduced Crescent Island at OCP 2025 and later shared full silicon details at Hot Chips 2026. The Xe3P design integrates 32 Xe cores plus 256 XMX engines. It leverages LPDDR5X rather than HBM, allowing the card to deploy within existing air-cooled server racks. Today’s announcement brings the official product name, confirmed bandwidth and compute specifications, plus verification that sample hardware has shipped to customers.

As a point of comparison, Intel’s current PCIe inference accelerator is Gaudi 3, equipped with 128GB HBM2e delivering 3.7TB/s bandwidth. Intel originally presented Crescent Island alongside Gaudi 3 rack designs during its OCP 2025 debut. The D-series takes a different memory approach: it offers nearly four times the per-card memory capacity, though its bandwidth falls to less than half that of Gaudi 3.

According to Intel, a single D-series card can run models with roughly up to 300 billion parameters, while an eight-GPU server can scale beyond one trillion parameters. The product is optimized for sustained multi-tenant inference and long-context agentic workloads, where KV cache expansion consumes memory faster than it increases compute demand. While its 1.5TB/s bandwidth trails HBM-based accelerators, Intel prioritizes capacity per watt and per dollar as the key metric for decode-heavy inference workloads, rather than peak bandwidth.

“Inference is becoming the defining AI workload, and enterprises need infrastructure that delivers the right performance at the right cost,” said Anil Nanduri, vice president of AI products and GTM at Intel’s Data Center Group. “With Intel GPU D-series, we’re focused on making high-capacity inference practical to deploy and economical to scale.” The software stack is built upon the unified Xe foundation, which Intel says enables binary portability across its GPU portfolio. Code developed for Arc Pro GPUs can run on the D-series without rewriting kernels.

Intel’s software stack combines upstream runtimes and serving frameworks for Xeon hosts paired with D-series accelerators. It includes Day 0 support for Meta’s Muse Glimmer, a 30-billion-parameter open-weight model built for local agentic AI tasks. Intel AI for Enterprise Agent Toolkit, already running on Xeon processors, uses a provider-based architecture that will target the D-series once hardware volume shipments begin. This means the orchestration layer will be ready before the accelerators reach mass deployment.

The partner slide shown during the keynote featured 53 logos covering AI-native firms, appliance vendors, software suppliers, neocloud operators and server OEM/ODM partners. Major server vendors include Dell, HPE, Lenovo, Supermicro, Cisco, ASUS, ASRock Rack, Giga Computing, MiTAC, Pegatron, QCT, Wistron, Inventec, Compal and Foxconn. Software partners are especially critical for a GPU marketed around cross-platform portability: Red Hat, Canonical, VMware by Broadcom, Nutanix, NetApp, WEKA, vLLM, Hugging Face, Anyscale and OpenHands are all on the list, while Astera Labs and Cornelis supply interconnect technology.

ORv3 Xeon Racks Scale Past 46,000 Cores

Alongside the new GPU, Intel showcased rack-scale systems built to the OCP Open Rack v3 specification, powered by Xeon 6 processors. Intel states the densest configurations deliver over 46,000 cores per rack with a total power draw of 133.45kW. This setup uses 160 sockets of the 288-core Xeon 6+, forming 80 dual-socket nodes inside a single rack, with each socket drawing approximately 834W including other rack components. Intel positions these racks to handle the CPU portion of agent pipelines: token routing, information retrieval, database queries, code execution, and feeding accelerators with sufficient I/O.

The partner slide lists ASRock Rack, ASUS, GIGABYTE, MiTAC Computing, MSI and Supermicro as vendors with available systems. Three of the six demonstrated racks follow the ORv3 standard, and the rest use traditional 19-inch enclosures. Intel argues the benchmark for AI racks is shifting toward how many concurrent agent tasks can run consistently under target latency constraints. “Agentic AI is changing what customers need from their data centers. It’s no longer enough to generate tokens faster. Infrastructure must orchestrate complex workflows, execute tasks, and deliver useful work efficiently at scale,” said Kevork Kechichian, executive vice president and general manager of Intel’s Data Center Group.

Open Adapter Card Work Continues at OCP

Intel also highlighted progress within the OCP Open Adapter Card workgroup, which it co-founded earlier this year together with AMD, Dell, NVIDIA and Qualcomm. The group is defining a sub-rack accelerator form factor that sits between standard PCIe cards and full rack-scale appliances. It standardizes mechanical dimensions, power delivery and out-of-band management interfaces, enabling multi-vendor accelerators to plug into the same open chassis.

The workgroup targets high-power adapters built for inference and mid-tier training platforms, compatible with both 19-inch and 21-inch racks. Intel and AMD are presenting progress on the specification during this week’s summit. Intel notes it has contributed 116 submissions to OCP since 2011. Nic Dubé’s keynote titled “Put Every Prompt in Its Place,” is scheduled for October 13 at 10:30 a.m. PT.

Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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